1. Field of the Invention
The present invention relates to a process of performing a laser repair process for memory device after formation of a solder bump.
2. Description of the Prior Art
High performance microelectronic devices often use solder balls or solder bumps for electrical and mechanical interconnection to other microelectronic devices. For instance, an ultra large scale integration (ULSI) chip may be electrically connected to a circuit board or other second stage packaging substrate by using solder balls or solder bumps. This connection technology is also referred to as “Flip-chip packaging, FC” technology.
Please refer to FIG. 1 to FIG. 4 of schematic views of performing a laser repair process for memory device on a semiconductor wafer 10 according to a prior art method. As shown in FIG. 1, the semiconductor wafer 10 comprises a substrate 12, which has an integrated circuit region (not shown) comprising an embedded memory array formed on its surface. The surface of the substrate 12 further comprises a bump pad 14, a plurality of fuses 16, and an alignment key 18. The bump pad 14 is electrically connected with the integrated circuit region. Therefore, after completing a subsequent packaging process, the integrated circuit is able to electrically connect to an external circuit through the bump pad 14. The fuses 16 are formed on an upper layer of the integrated circuit region and electrically connected with the embedded memory, and after finding invalid memory cells, word lines, or conducting wires within the embedded memory by performing a circuit probing process, a laser repair process is performed to eliminate these invalid elements by cutting off the corresponding fuses.
The prior art method is first forming a first dielectric layer 20 on the surface of the semiconductor wafer 10, which completely covers the bump pad 14 and the fuses 16. The first dielectric layer 20 is also called a passivation layer and is used to seal up and to avoid moistness. Thereafter, a photo-etching-process (PEP) is performed to form a contact hole 21 in the first dielectric layer 20 above the bump pad 14 so as to expose portions of the bump pad 14. Because a subsequent laser repair process uses laser beams to penetrate and to cut off portions of the fuses 16, the first dielectric layer 20 must be composed of transparent materials. As shown in FIG. 2, a circuit probing process is then performed, which uses a probing tip (not shown) electrically connected to the bump pad 14 to find invalid memory cells, word lines, or conducting wires within the embedded memory in the integrated circuit region, and the alignment key 18 is used to define the regions needed to accept laser repair. After that, an accurate laser zip process is performed to cut off portions of the fuses 16 in the regions defined by the alignment key 18 so as to destroy electrical connections of these invalid elements.
As shown in FIG. 3, a second dielectric layer 22 composed of benzocyclobutene (BCB), polyimide (PI), or BCB+PI is formed on the surface of the semiconductor wafer 10. Then, as shown in FIG. 4, an under bump metallurgy (UBM) process is performed to form a metal layer 24, which is composed of specific multi-layer metal films, on a surface of the contact hole 21 by sputtering. The functions of the metal layer 24 comprise providing adhesion and diffusion barrier, improving moistness of the bump pad 14, and preventing oxidation. A solder bump 26 is then formed on the metal layer 24 corresponding to the contact hole 21 by evaporating, printing, electro-plating, dipping, or ultrasonic soldering. Finally, the semiconductor wafer 10 is placed on a packaging board (not shown), and the solder bump 26 melted by a thermal treatment generates surface tension to connect the semiconductor wafer 10 and the packaging board.
The prior art method causes several problems as a result of performing the circuit probing and laser repair process before forming the second dielectric layer 22 and the metal layer 24. First, the circuit probing process using the probing tip directly connected to the bump pad 14 may form a serious probing mark on a surface of the bump pad 14. Because the metal layer 24 formed on the surface of the bump pad 14 has poor step coverage, the probing mark on the surface of the bump pad 14 may cause the metal layer 24 to lose or reduce its functions of providing adhesion and diffusion barrier. Additionally, when an interconnect system uses a cooper process and low-k materials as insulation layers, the circuit probing process directly performed on the bump pad 14 may result in bare copper or crack insulation layers because of excess probing force. As well, oxidation of the probing mark on the surface of the bump pad 14 is a difficult problem.
Furthermore, because the laser repair process performed after the circuit probing process cuts off portions of the fuses 16, a plurality of trenches 27 with high aspect ratio are formed on the surface of the semiconductor wafer 10. When filling the trenches 27 with the second dielectric layer 22, some voids may be formed in the second dielectric layer 22 and affect the reliability of products.